AI SearchTCP/IP stack chip processor
Call Number: AIT Thesis no.ME-03-02 Material type:
SeriesSeries: Asian Institute of Technology. Thesis ; no. ME-03-02Publication details: Bangkok : Asian Institute of Technology, 2003Description: 60, 22, 30, 26, 8, 8 pSubject(s): Online resources: Dissertation note: Thesis (M.Eng.) - Asian Institute of Technology, 2003 Summary: In the past 3 - 4 years, the Internet technology has continuously changed and revolved, enabling it to be used for a wide variety of purposes. Nowadays, many of the home appliances are using the Internet technology to facilitate an easier control and communication between appliances. This thesis covers this area of Internet technology with the aim of compressing this technology into a single chip, called "Internet Chip Processing". However due to the limited resources and the complexity of the process, the thesis therefore has divided such process into two major sections. The first section is processed on the Microprocessor Unit by approaching the Application Layer, the Transport Layer, and the Network Layer, which is a major part of the Internet Technology. On the other hand, the second section is processed on FPGA chip in the area of the Datalink Layer, of which is the most complex and imp01tant layer compare to the other layers of the Internet Technology. This specific layer operates by detecting the received data information and ensuring that it is accurate. It also manager the signal formats that are to sent to the Physical Interface and then to the Internet Line. As a result, this is quite crucial as if the process in this area fails, the entire network will therefore breakdown. Nevertheless, regardless of this complexity, one can always combine this aforementioned together into one single chip when IP Core of a Microprocessor Unit is available. Base on the study of this thesis, most of the processes are run on the Application Layer, the Transport Layer, and the Network Layer of the Microprocessor Unit that consumers a significant amount of space and process time. In the future, to reduce the time and space consumption of the process, it is recommended that the Transport Layer and the Network Layer be place on the FPGA chip with the Datalink Layer.
| Cover image | Item type | Current library | Home library | Collection | Shelving location | Call number | Materials specified | Vol info | URL | Copy number | Status | Notes | Date due | Barcode | Item holds | Item hold queue priority | Course reserves | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
22-AIT Thesis (Replacement)
|
Asian Institute of Technology Library AIT Publications | AIT Thesis no.ME-03-02 (Browse shelf(Opens below)) | 3 | Available | 30050120658025 | |||||||||||||
40-Archives
|
Asian Institute of Technology Library Archives | AIT Thesis no.ME-03-02 (Browse shelf(Opens below)) | 1 | Available | 30050160028196 |
Thesis (M.Eng.) - Asian Institute of Technology, 2003
A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies
In the past 3 - 4 years, the Internet technology has continuously changed and revolved, enabling it to be used for a wide variety of purposes. Nowadays, many of the home appliances are using the Internet technology to facilitate an easier control and communication between appliances. This thesis covers this area of Internet technology with the aim of compressing this technology into a single chip, called "Internet Chip Processing". However due to the limited resources and the complexity of the process, the thesis therefore has divided such process into two major sections. The first section is processed on the Microprocessor Unit by approaching the Application Layer, the Transport Layer, and the Network Layer, which is a major part of the Internet Technology. On the other hand, the second section is processed on FPGA chip in the area of the Datalink Layer, of which is the most complex and imp01tant layer compare to the other layers of the Internet Technology. This specific layer operates by detecting the received data information and ensuring that it is accurate. It also manager the signal formats that are to sent to the Physical Interface and then to the Internet Line. As a result, this is quite crucial as if the process in this area fails, the entire network will therefore breakdown. Nevertheless, regardless of this complexity, one can always combine this aforementioned together into one single chip when IP Core of a Microprocessor Unit is available. Base on the study of this thesis, most of the processes are run on the Application Layer, the Transport Layer, and the Network Layer of the Microprocessor Unit that consumers a significant amount of space and process time. In the future, to reduce the time and space consumption of the process, it is recommended that the Transport Layer and the Network Layer be place on the FPGA chip with the Datalink Layer.
There are no comments on this title.