Extension of analysis interpretive treatise (AIT) package to design capabilities

By: Call Number: AIT Thesis no. ST-81-04 Contributor(s): Material type: TextSeries: Asian Institute of Technology. Thesis ; no. ST-81-04Publication details: Bangkok : Asian Institute of Technology, 1981Description: iv, 109 pSubject(s): Online resources: Dissertation note: Thesis (M.Eng.) - Asian Institute of Technology, 1981 Summary: The concept of database is employed in the development of AIT (Analysis Interpretive Treatise). Existing capabilities includes: 1) Matrix manipulation and operations: 2) Generation of characteristic arrays of a finite element mesh; 3) Finite element processes, e.g . element stiffness assembling, static condensation, sub structuring, eigenvalue solution. A scheme for implementing the design capability is presented here, and processors for the design of reinforced concrete frame structure are developed. Documentation of modified processors and new processors is given. A three-story building is used to illustrate the design capability of the program.
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22-AIT Thesis (Replacement) Asian Institute of Technology Library AIT Publications AIT Thesis no. ST-81-04 (Browse shelf(Opens below)) 3 Available 30050120697577
40-Archives Asian Institute of Technology Library Archives AIT Thesis no. ST-81-04 (Browse shelf(Opens below)) 1 Available 30050160013768

A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering. School of Engineering and Technology

Thesis (M.Eng.) - Asian Institute of Technology, 1981

The concept of database is employed in the development of AIT (Analysis Interpretive Treatise). Existing capabilities includes: 1) Matrix manipulation and operations: 2) Generation of characteristic arrays of a finite element mesh; 3) Finite element processes, e.g . element stiffness assembling, static condensation, sub structuring, eigenvalue solution. A scheme for implementing the design capability is presented here, and processors for the design of reinforced concrete frame structure are developed. Documentation of modified processors and new processors is given. A three-story building is used to illustrate the design capability of the program.

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