AlteraNet : (Record no. 4037)

MARC details
000 -LEADER
fixed length control field 03726nas a2200433 a 4500
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20260817162138.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 201117s2018 th u m rtt 000 a eng d
035 ## - SYSTEM CONTROL NUMBER
System control number .b12298803
099 #9 - LOCAL FREE-TEXT CALL NUMBER (OCLC)
Classification number AIT Caps. Proj. no.EL-18-02
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name De Soysa, Warusha H.A.C.C.
245 10 - TITLE STATEMENT
Title AlteraNet :
Remainder of title optimized processing architecture for hardware accelerating of convolutional neural nets
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Pathum Thani :
Name of publisher, distributor, etc. Asian Institute of Technology,
Date of publication, distribution, etc. 2018
300 ## - PHYSICAL DESCRIPTION
Extent 49 leaves :
Other physical details ill. (some col.) +
Accompanying material 1 online resource
490 1# - SERIES STATEMENT
Series statement Caps. Proj. ;
Volume/sequential designation no. EL-18-02
500 ## - GENERAL NOTE
General note A capstone project report submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Engineering Electronics Engineering, School of Engineering and Technology
502 ## - DISSERTATION NOTE
Dissertation note Capstone Project (B.Sc.)-Asian Institute of Technology, 2018
520 ## - SUMMARY, ETC.
Summary, etc. Convolutional Neural Networks (CNNs/ ConvNet) being the AI systems for their superior accuracy mainly plays a key role in many modern-day application segments such as Computer Vision, image classification, Surveillance, speech recognition, Machine Vision, Robotics. Conventional sequential processing on software with a general-purpose CPU has become significantly insufficient due to the high demand of processing power to deliver adequate throughput and performance. Therefore, the reason of cost, energy efficiency, reconfigurable performance and some available tools that can speed up verification and flow implementa- tion, such as OpenCL (Open Computing Language) based high level synthesis over GPU, recently oppose Field-Programmable gate array (FPGA) as CNN accelerator. In this paper, I expose Hardware Accelerating of CNNs, a fast and adequate FPGA accelerator imple- mented on Altera DEI System-on-Chip(SoC), FPGA Platform with high performance and less power dissipation. The AlteraNet CNN consist of customized and optimized topologies in CNN and designed for classification image by using ImageNet with 80.3% top 5 accuracy and 57.] % top ] accuracy gained from complex computations of 527 million multiply accumulates process. The AlteraNet FPGA accelerator grant adequate evaluation of AlteraNet CNN. It used nested loop algorithm to accelerates full network, which minimize the number of memory ac- cesses and arithmetic operations. The AlteraNet FPGA accelerator using High Level Synthe- sis(HLS) on the Altera DEI-SoC, and usage is devise utilization of 81 % with clock frequency of 300M Hz.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Hardware accelerated
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Artificial intelligence
General subdivision Data processing
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Convolutions (Mathematics)
General subdivision Data processing
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Neural networks (Computer science)
700 0# - ADDED ENTRY--PERSONAL NAME
Personal name Mongkol Ekpanyapong,
Relator term Chairperson
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Dailey, Mathew N.,
Relator term Examination Committee
810 2# - SERIES ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element Asian Institute of Technology.
Title of a work Caps. Proj. ;
Volume/sequential designation no. EL-18-02
856 ## - ELECTRONIC LOCATION AND ACCESS
Materials specified Full-Text
Uniform Resource Identifier <a href="http://203.159.5.9/ait-thesis/detail.php?q=B14014">http://203.159.5.9/ait-thesis/detail.php?q=B14014</a>
907 ## - LOCAL DATA ELEMENT G, LDG (RLIN)
a .b12298803
b mnait
c m
902 ## - LOCAL DATA ELEMENT B, LDB (RLIN)
a 240411
998 ## - LOCAL CONTROL INFORMATION (RLIN)
Operator's initials, OID (RLIN) 0
Cataloger's initials, CIN (RLIN) 201117
First date, FD (RLIN) m
-- a
-- m
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945 ## - LOCAL PROCESSING INFORMATION (OCLC)
l mnait
945 ## - LOCAL PROCESSING INFORMATION (OCLC)
l mnarc
945 ## - LOCAL PROCESSING INFORMATION (OCLC)
l mnarc
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type 40-Archives
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type 61-CD-ROM
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type 20-AIT Publication
909 ## - LOCAL ITEMS USED
Barcode Barcode : 30050120884175
CREATED CREATED : 2019-03-18
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909 ## - LOCAL ITEMS USED
Barcode Barcode : 30050120974513
CREATED CREATED : 2020-11-17
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Holdings
Withdrawn status Lost status Damaged status Not for loan Home library Current library Shelving location Date acquired Total checkouts Full call number Barcode Date last seen Copy number Price effective from Koha item type Cost, normal purchase price
      Available for Loans Asian Institute of Technology Library Asian Institute of Technology Library Archives 17/08/2026   AIT Caps. Proj. no.EL-18-02 30050120884175 17/08/2026 1 17/08/2026 40-Archives  
      Available for Loans Asian Institute of Technology Library Asian Institute of Technology Library Archives 17/08/2026   AIT Caps. Proj. no.EL-18-02   17/08/2026   17/08/2026 61-CD-ROM  
      Available for Loans Asian Institute of Technology Library Asian Institute of Technology Library AIT Publications 17/08/2026   AIT Caps. Proj. no.EL-18-02 30050120974513 17/08/2026 1 17/08/2026 20-AIT Publication 50.00
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