AI SearchA design of array multiplier
Call Number: AIT Thesis no. CS-95-24 Material type:
TextSeries: Asian Institute of Technology. Thesis ; no. CS-95-24Publication details: Bangkok : Asian Institute of Technology, 1995Description: 38 leaves + 1 online resourceSubject(s): Online resources: Dissertation note: Thesis (M.Sc.) - Asian Institute of Technology, 1995 Summary: In this thesis, a new design technique, 3n-2m scheme, for array multipliers is presented. Its efficiency and flexibility are analyzed. Comparison with existing designs is discussed. The author also provides its application to some existing array multiplier technique for faster speed. The design to combine multiplication with addition is implemented on the basis of existing multiplier technique and new proposed 3n-2m scheme.
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Asian Institute of Technology Library Archives | AIT Thesis no. CS-95-24 (Browse shelf(Opens below)) | Available | 30050120356174 |
A thesis submitted in partial fulfilment of the requirement for the degree of Master of Science
Thesis (M.Sc.) - Asian Institute of Technology, 1995
In this thesis, a new design technique, 3n-2m scheme, for array multipliers is presented. Its efficiency and flexibility are analyzed. Comparison with existing designs is discussed. The author also provides its application to some existing array multiplier technique for faster speed. The design to combine multiplication with addition is implemented on the basis of existing multiplier technique and new proposed 3n-2m scheme.
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