AI SearchTurbo decoder core design
Call Number: AIT Thesis no.ME-01-03 Material type:
SeriesSeries: Asian Institute of Technology. Thesis ; no. ME-01-03Publication details: Bangkok : Asian Institute of Technology, 2001Description: 36 pSubject(s): Online resources: Dissertation note: Thesis (M.Eng.) - Asian Institute of Technology, 2001 Summary: The usage of channel coding improves the error performance of communication systems but the transmission of additional bit results in a reduction in bandwidth efficiency. Turbo coding has been one of the best coding techniques because it provides the error correction capability near Shannon's limit. C.Berrou, A.Glavieux and P.Thitimajshima introduced turbo codes in 1993, then it is widely used in wireless communication applications, satellite or deep space communication applications and magnetic storage applications. The turbo codes of 3GPP wireless communication standard is concentrated in this thesis, because of designing the turbo decoder for decoding this specific turbo codes is objective of the thesis. The hardware model of the turbo decoder is designed by describing behavior and strncture of decoding algorithm in VHDL, and simulating the function of the designed model. Since algorithm for decoding the turbo codes is complexity for implementation in hardware and VHDL description is the design entry of hardware implementation. Therefore Max-Log-MAP algorithm is chosen for implementation in hardware model. The hardware model of the turbo decoder will be synthesized and implemented on FPGA chip or ASIC depend on usage.
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22-AIT Thesis (Replacement)
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Asian Institute of Technology Library AIT Publications | AIT Thesis no.ME-01-03 (Browse shelf(Opens below)) | 3 | Available | 30050120657852 | |||||||||||||
40-Archives
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Asian Institute of Technology Library Archives | AIT Thesis no.ME-01-03 (Browse shelf(Opens below)) | 1 | Available | 30050160027818 | |||||||||||||
20-AIT Publication
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Asian Institute of Technology Library AIT Publications | AIT Thesis no.ME-01-03 (Browse shelf(Opens below)) | 1 | Available | 30050211024491 |
A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies
Thesis (M.Eng.) - Asian Institute of Technology, 2001
The usage of channel coding improves the error performance of communication systems but the transmission of additional bit results in a reduction in bandwidth efficiency. Turbo coding has been one of the best coding techniques because it provides the error correction capability near Shannon's limit. C.Berrou, A.Glavieux and P.Thitimajshima introduced turbo codes in 1993, then it is widely used in wireless communication applications, satellite or deep space communication applications and magnetic storage applications. The turbo codes of 3GPP wireless communication standard is concentrated in this thesis, because of designing the turbo decoder for decoding this specific turbo codes is objective of the thesis. The hardware model of the turbo decoder is designed by describing behavior and strncture of decoding algorithm in VHDL, and simulating the function of the designed model. Since algorithm for decoding the turbo codes is complexity for implementation in hardware and VHDL description is the design entry of hardware implementation. Therefore Max-Log-MAP algorithm is chosen for implementation in hardware model. The hardware model of the turbo decoder will be synthesized and implemented on FPGA chip or ASIC depend on usage.
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