AI SearchA 12-bit low voltage continuous-time delta-sigma modulator
Call Number: AIT Thesis no.ME-06-01 Material type:
SeriesSeries: Asian Institute of Technology. Thesis ; no. ME-06-01Publication details: Pathum Thani, Thailand : Asian Institute of Technology, 2006Description: 50 p. : illSubject(s): Online resources: Dissertation note: Thesis (M.Eng.) - Asian Institute of Technology, 2006 Summary: This thesis work implements a third order low-pass delta-sigma modulator using a continuous-time (CT) loop filter. The loop filter is realized by using active RC integrators. The integrators use fully differential folded cascode OTA for low voltage application. The OTA has dc gain of 63.5 dB and unity gain bandwidth of 9 MHz. The sampling and quantization is performed by a latched type clocked comparator. For the low-voltage and high sp:.d comparator, a fully symmetrical regenerative comparator is used. The comparator has the worst case signal-dependent delay, td below 1% Ts which has no significant influence on the overall modulator performance. The output of the comparator is stored in D-flip-flop. The feedback DAC is implemented with NRZ DAC which consists of the traditional clock generator and switching block which follows the flip-flop output. The DAC has slew rate of 274 V/las. The modulator is implemented in a UMC 1.8 V, 0.18 pm CMOS technology. Calculations of the low-power CT A-Z modulator show a dynamic range and peak SNDR of 75 dB and 67 dB, respectively, in a bandwidth of 25 kHz and oversampling frequency of 2.4 MHz. The measured power is only 120 pW from a single 1 V supply
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A thesis submitted in pa1tial fulfillment of the requirements for the degree of Master of Engineering, School of Engineering and Technology
Thesis (M.Eng.) - Asian Institute of Technology, 2006
This thesis work implements a third order low-pass delta-sigma modulator using a continuous-time (CT) loop filter. The loop filter is realized by using active RC integrators. The integrators use fully differential folded cascode OTA for low voltage application. The OTA has dc gain of 63.5 dB and unity gain bandwidth of 9 MHz. The sampling and quantization is performed by a latched type clocked comparator. For the low-voltage and high sp:.d comparator, a fully symmetrical regenerative comparator is used. The comparator has the worst case signal-dependent delay, td below 1% Ts which has no significant influence on the overall modulator performance. The output of the comparator is stored in D-flip-flop. The feedback DAC is implemented with NRZ DAC which consists of the traditional clock generator and switching block which follows the flip-flop output. The DAC has slew rate of 274 V/las. The modulator is implemented in a UMC 1.8 V, 0.18 pm CMOS technology. Calculations of the low-power CT A-Z modulator show a dynamic range and peak SNDR of 75 dB and 67 dB, respectively, in a bandwidth of 25 kHz and oversampling frequency of 2.4 MHz. The measured power is only 120 pW from a single 1 V supply
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