AI SearchClock and data recovery for SONET OC-12 system
Call Number: AIT Thesis no.ME-05-06 Material type:
SeriesSeries: Asian Institute of Technology. Thesis ; no. ME-05-06Publication details: Pathum Thani, Thailand : Asian Institute of Technology, 2005Description: 47 p. : illSubject(s): Online resources: Dissertation note: Thesis (M.Eng.) - Asian Institute of Technology, 2005 Summary: This thesis describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. The CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. The schematics are implemented in C11 (0.13 æm CMOS). One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external capacitor loop filter.
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A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies
Thesis (M.Eng.) - Asian Institute of Technology, 2005
This thesis describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. The CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. The schematics are implemented in C11 (0.13 æm CMOS). One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external capacitor loop filter.
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