AI SearchNoise reduction system for digital hearing aid
Call Number: AIT Thesis no.ME-07-06 Material type:
SeriesSeries: Asian Institute of Technology. Thesis ; no. ME-07-06Publication details: Pathum Thani, Thailand : Asian Institute of Technology, 2007Description: 84 p. : illSubject(s): Online resources: Dissertation note: Thesis (M.Sc.) - Asian Institute of Technology, 2007 Summary: One of the major problems for hearing aid users is surrounding noise. The thesis objective is to design noise reduction hardware (integrated circuit) for digital hearing aids. Instead of relying on separate algorithm and hardware (integrated circuit) developments, a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time is illustrated. A noise reduction core using ADMA adaptive Beamformer is designed and tested as an example
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A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Microelectronics, School of Engineering and Technology
Thesis (M.Sc.) - Asian Institute of Technology, 2007
One of the major problems for hearing aid users is surrounding noise. The thesis objective is to design noise reduction hardware (integrated circuit) for digital hearing aids. Instead of relying on separate algorithm and hardware (integrated circuit) developments, a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time is illustrated. A noise reduction core using ADMA adaptive Beamformer is designed and tested as an example
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