Tom Takan creator Lertsak Lekawat Chairperson Afzulpurkar, Nitin V. Examination Committee Dutta, Joydeep Examination Committee Chumnarn Punyasai Examination committee Asian Institute of Technology Fellowship Scholarship donor text series technical report th Pathum Thani, Thailand Asian Institute of Technology 2005 continuing eng 47 p. : ill. This thesis describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. The CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. The schematics are implemented in C11 (0.13 æm CMOS). One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external capacitor loop filter. A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies Thesis (M.Eng.) - Asian Institute of Technology, 2005 SONET (Data transmission) Data recovery (Computer science) Data transmission systems Metal oxide semiconductors, Complementary Asian Institute of Technology. http://203.159.5.9/ait-thesis/detail.php?q=B09817 http://203.159.5.9/ait-thesis/detail.php?q=B09817 060223 20260817172935.0