A Chen, Peng creator Yulu, Qi Chairperson Murai, Shunji Examination committee Huynh, Ngoc Phien Examination Committee SEC Scholarship donor text th Bangkok Asian Institute of Technology 1995 monographic eng

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38 leaves + 1 online resource In this thesis, a new design technique, 3n-2m scheme, for array multipliers is presented. Its efficiency and flexibility are analyzed. Comparison with existing designs is discussed. The author also provides its application to some existing array multiplier technique for faster speed. The design to combine multiplication with addition is implemented on the basis of existing multiplier technique and new proposed 3n-2m scheme. A thesis submitted in partial fulfilment of the requirement for the degree of Master of Science Thesis (M.Sc.) - Asian Institute of Technology, 1995 Multiplication Asian Institute of Technology. http://203.159.5.9/ait-thesis/detail.php?q=B15030 http://203.159.5.9/ait-thesis/detail.php?q=B15030 080998 20260818090226.0