03726nas a2200433 a 4500 20260817162138.0 201117s2018 th u m rtt 000 a eng d .b12298803 AIT Caps. Proj. no.EL-18-02 De Soysa, Warusha H.A.C.C. AlteraNet : optimized processing architecture for hardware accelerating of convolutional neural nets Pathum Thani : Asian Institute of Technology, 2018 49 leaves : ill. (some col.) + 1 online resource Caps. Proj. ; no. EL-18-02 A capstone project report submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Engineering Electronics Engineering, School of Engineering and Technology Capstone Project (B.Sc.)-Asian Institute of Technology, 2018 Convolutional Neural Networks (CNNs/ ConvNet) being the AI systems for their superior accuracy mainly plays a key role in many modern-day application segments such as Computer Vision, image classification, Surveillance, speech recognition, Machine Vision, Robotics. Conventional sequential processing on software with a general-purpose CPU has become significantly insufficient due to the high demand of processing power to deliver adequate throughput and performance. Therefore, the reason of cost, energy efficiency, reconfigurable performance and some available tools that can speed up verification and flow implementa- tion, such as OpenCL (Open Computing Language) based high level synthesis over GPU, recently oppose Field-Programmable gate array (FPGA) as CNN accelerator. In this paper, I expose Hardware Accelerating of CNNs, a fast and adequate FPGA accelerator imple- mented on Altera DEI System-on-Chip(SoC), FPGA Platform with high performance and less power dissipation. The AlteraNet CNN consist of customized and optimized topologies in CNN and designed for classification image by using ImageNet with 80.3% top 5 accuracy and 57.] % top ] accuracy gained from complex computations of 527 million multiply accumulates process. The AlteraNet FPGA accelerator grant adequate evaluation of AlteraNet CNN. It used nested loop algorithm to accelerates full network, which minimize the number of memory ac- cesses and arithmetic operations. The AlteraNet FPGA accelerator using High Level Synthe- sis(HLS) on the Altera DEI-SoC, and usage is devise utilization of 81 % with clock frequency of 300M Hz. Hardware accelerated Artificial intelligence Data processing Convolutions (Mathematics) Data processing Neural networks (Computer science) Mongkol Ekpanyapong, Chairperson Dailey, Mathew N., Examination Committee Asian Institute of Technology. Caps. Proj. ; no. EL-18-02 Full-Text http://203.159.5.9/ait-thesis/detail.php?q=B14014 .b12298803 mnait m 240411 0 201117 m a m 0 mnait mnarc mnarc 40 61 20 Barcode : 30050120884175 CREATED : 2019-03-18 RECORD # : i13160618 LPATRON : 0 LCHKIN : - # RENEWALS : 0 # OVERDUE : 0 IUSE3 : 0 TOT CHKOUT : 0 TOT RENEW : 0 Barcode : - CREATED : 2019-03-18 RECORD # : i1316062x LPATRON : 0 LCHKIN : - # RENEWALS : 0 # OVERDUE : 0 IUSE3 : 0 TOT CHKOUT : 0 TOT RENEW : 0 Barcode : 30050120974513 CREATED : 2020-11-17 RECORD # : i1331094x LPATRON : 0 LCHKIN : - # RENEWALS : 0 # OVERDUE : 0 IUSE3 : 0 TOT CHKOUT : 0 TOT RENEW : 0 4037 4037 0 0 0 0 MAIN MAIN mnarc 2026-08-17 0 AIT Caps. Proj. no.EL-18-02 30050120884175 2026-08-17 16:21:38 1 2026-08-17 40 0 0 0 0 MAIN MAIN mnarc 2026-08-17 0 AIT Caps. Proj. no.EL-18-02 2026-08-17 16:21:38 2026-08-17 61 0 0 0 0 MAIN MAIN mnait 2026-08-17 50.00 0 AIT Caps. Proj. no.EL-18-02 30050120974513 2026-08-17 16:21:38 1 2026-08-17 20