04247nas|a2200457 i 4500 20260818171535.0 030926s2002 th u m rtt 00| a1eng d .b11900210 AIT Thesis no.TC-02-08 Mansur, Al Performance evaluation of Dual-Banyan ATM switch Bangkok : Asian Institute of Technology, 2002 62 leaves Thesis ; no. TC-02-08 A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Engineering and Technology Thesis (M.Eng.) - Asian Institute of Technology, 2002 Buffered Banyan network based ATM switches, which have been studied extensively in the recent past, are popular among switch designs because of their self-routing property, high degree of parallelism, regularity in architecture, constant delay for all input-output port pairs, in-order delivery of cells, and suitability for VLSI implementation. The performances of Dual-Banyan (DB) switch, internally speeded-up and dual planed DB switch have been studied in this thesis. Simulation tool for evaluating the performance of these three switches was developed. Switch performances are evaluated under uniform and single-source-to-single-destination traffic pattern where the cell arrival is modeled according to Bernoulli and Interrupted Bernoulli process. Maximum throughput is found to be only 0.25 in Dual-Banyan switch under Bernoulli arrival and maximum conflict traffic pattern whereas maximum throughput is about 0.5 in speeded-up switch and in dual plane switch under the same input traffic. Under bursty input traffic, it is found that dual plane switch has better throughput performance than other two architectures. Mean delay performance of the speeded-up switch and the dual plane switch is almost similar and is better than that of DB switch. For buffer size of eight in each switching stage and offered traffic load of 0.9, throughput is about 0.7, 0.6 and 0.5 in dual plane, speeded-up and DB switch respectively. It is observed that cell loss in each switching stage is different and depends on the input traffic and buffer size. In a DB switch, the stage at which largest cell lost occurs shifts with the increase of buffer for uniform traffic of moderate load. Under maximum conflict traffic pattern, the second stage has the highest loss and switch throughput is mostly determined by this stage in all three switches of size 32x32. Speeded-up switch has largest cell loss in its last stage and blocking is reduced significantly when more buffers are allocated in the last stage. For studied cases with a given input traffic and total buffer, buffer combinations for minimum blocking have been found. Asynchronous transfer mode Telecommunication Switching systems Erke, Tapio J., Chairperson Ahmed, Kazi Mohiuddin, Examination Committee Fernando, W.A.C., Examination Committee Government of Finland, Scholarship donor Asian Institute of Technology. Thesis ; no. TC-02-08 Full-Text http://203.159.5.9/ait-thesis/detail.php?q=B07559 .b11900210 mnait u 240710 0 030926 m a u 0 mnait mnait mnarc mnarc 22 40 20 Barcode : 30050120809784 CREATED : 2014-10-04 RECORD # : i12789422 LPATRON : 0 LCHKIN : - # RENEWALS : 0 # OVERDUE : 0 IUSE3 : 1 TOT CHKOUT : 0 TOT RENEW : 0 Barcode : 30050160045026 CREATED : 2016-03-03 RECORD # : i12888886 LPATRON : 0 LCHKIN : - # RENEWALS : 0 # OVERDUE : 0 IUSE3 : 0 TOT CHKOUT : 0 TOT RENEW : 0 Barcode : 30050211033526 CREATED : 2021-05-05 RECORD # : i13344754 LPATRON : 0 LCHKIN : - # RENEWALS : 0 # OVERDUE : 0 IUSE3 : 0 TOT CHKOUT : 0 TOT RENEW : 0 Barcode : 30050211033518 CREATED : 2021-05-05 RECORD # : i13344766 LPATRON : 0 LCHKIN : - # RENEWALS : 0 # OVERDUE : 0 IUSE3 : 0 TOT CHKOUT : 0 TOT RENEW : 0 86637 86637 0 0 0 0 MAIN MAIN mnarc 2026-08-18 50.00 0 AIT Thesis no.TC-02-08 30050120809784 2026-08-18 17:15:35 3 2026-08-18 22 0 0 0 0 MAIN MAIN mnarc 2026-08-18 0 AIT Thesis no.TC-02-08 30050160045026 2026-08-18 17:15:35 2026-08-18 40 0 0 0 0 MAIN MAIN mnait 2026-08-18 50.00 0 AIT Thesis no.TC-02-08 30050211033526 2026-08-18 17:15:35 1 2026-08-18 20 0 0 0 0 MAIN MAIN mnait 2026-08-18 50.00 0 AIT Thesis no.TC-02-08 30050211033518 2026-08-18 17:15:35 2 2026-08-18 20