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008 060223s2005 th uu|m rtt 0| a1eng d
035 _a.b11981520
099 9 _aAIT Thesis no.ME-05-06
100 0 _aTom Takan
245 1 0 _aClock and data recovery for SONET OC-12 system
260 _aPathum Thani, Thailand :
_bAsian Institute of Technology,
_c2005
300 _a47 p. :
_bill.
490 1 _aThesis ;
_vno. ME-05-06
500 _aA thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies
502 _aThesis (M.Eng.) - Asian Institute of Technology, 2005
520 _aThis thesis describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. The CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. The schematics are implemented in C11 (0.13 æm CMOS). One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external capacitor loop filter.
650 0 _aSONET (Data transmission)
650 0 _aData recovery (Computer science)
650 0 _aData transmission systems
650 0 _aMetal oxide semiconductors, Complementary
700 0 _aLertsak Lekawat,
_eChairperson
700 1 _aAfzulpurkar, Nitin V.,
_eExamination Committee
700 1 _aDutta, Joydeep,
_eExamination Committee
700 0 _aChumnarn Punyasai,
_eExamination committee
710 2 _aAsian Institute of Technology Fellowship,
_eScholarship donor
810 2 _aAsian Institute of Technology.
_tThesis ;
_vno. ME-05-06
856 _3Full-Text
_uhttp://203.159.5.9/ait-thesis/detail.php?q=B09817
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