000			03726nas a2200433 a 4500
005			20260817162138.0
008			201117s2018 th u m rtt 000 a eng d
035			_a.b12298803
099		9	_aAIT Caps. Proj. no.EL-18-02
100	1		_aDe Soysa, Warusha H.A.C.C.
245	1	0	_aAlteraNet : _boptimized processing architecture for hardware accelerating of convolutional neural nets
260			_aPathum Thani : _bAsian Institute of Technology, _c2018
300			_a49 leaves : _bill. (some col.) + _e1 online resource
490	1		_aCaps. Proj. ; _vno. EL-18-02
500			_aA capstone project report submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Engineering Electronics Engineering, School of Engineering and Technology
502			_aCapstone Project (B.Sc.)-Asian Institute of Technology, 2018
520			_aConvolutional Neural Networks (CNNs/ ConvNet) being the AI systems for their superior accuracy mainly plays a key role in many modern-day application segments such as Computer Vision, image classification, Surveillance, speech recognition, Machine Vision, Robotics. Conventional sequential processing on software with a general-purpose CPU has become significantly insufficient due to the high demand of processing power to deliver adequate throughput and performance. Therefore, the reason of cost, energy efficiency, reconfigurable performance and some available tools that can speed up verification and flow implementa- tion, such as OpenCL (Open Computing Language) based high level synthesis over GPU, recently oppose Field-Programmable gate array (FPGA) as CNN accelerator. In this paper, I expose Hardware Accelerating of CNNs, a fast and adequate FPGA accelerator imple- mented on Altera DEI System-on-Chip(SoC), FPGA Platform with high performance and less power dissipation. The AlteraNet CNN consist of customized and optimized topologies in CNN and designed for classification image by using ImageNet with 80.3% top 5 accuracy and 57.] % top ] accuracy gained from complex computations of 527 million multiply accumulates process. The AlteraNet FPGA accelerator grant adequate evaluation of AlteraNet CNN. It used nested loop algorithm to accelerates full network, which minimize the number of memory ac- cesses and arithmetic operations. The AlteraNet FPGA accelerator using High Level Synthe- sis(HLS) on the Altera DEI-SoC, and usage is devise utilization of 81 % with clock frequency of 300M Hz.
650		0	_aHardware accelerated
650		0	_aArtificial intelligence _xData processing
650		0	_aConvolutions (Mathematics) _xData processing
650		0	_aNeural networks (Computer science)
700	0		_aMongkol Ekpanyapong, _eChairperson
700	1		_aDailey, Mathew N., _eExamination Committee
810	2		_aAsian Institute of Technology. _tCaps. Proj. ; _vno. EL-18-02
856			_3Full-Text _uhttp://203.159.5.9/ait-thesis/detail.php?q=B14014
907			_a.b12298803 _bmnait _cm
902			_a240411
998			_b0 _c201117 _dm _ea _fm _g0
945			_lmnait
945			_lmnarc
945			_lmnarc
942			_c40
942			_c61
942			_c20
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