000			03869nas a2200385 a 4500
005			20260817161120.0
008			090414s2007 th uu|m rtt 0| a1eng d
035			_a.b12052590
099		9	_aAIT Thesis no.ME-07-05
100	1		_aHasan, Md. Arif
245	1	0	_a1 volt based frequency synthesizer design for 2.4 GHz ISM band
260			_aPathum Thani, Thailand : _bAsian Institute of Technology, _c2007
300			_a112 p. : _bill.
490	1		_aThesis ; _vno. ME-07-05
500			_aA thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Microelectronics, School of Engineering and Technology
502			_aThesis (M.Sc.) - Asian Institute of Technology, 2007
520			_a Wireless communication has undergone an unbelievable development over the past few years. The rapid development of wireless communication has lead to an increasing demand of low-cost, low-power and high-performance Integrated Circuits (ICs). Short Communication Network, Bluetooth or Wireless Local Area Network (WLAN), Zigbee has replaced the old cable communication. New low-power, low-rate standards, such as Bluetooth or Zigbee, imposes new area and power reduction constraints due to its main fields of application. Area, cost and power constraints may be solved by means of integrating the digital and RF sections of these transceivers with the same well-known CMOS technology. In order to meet the growing demand for these short wireless communication networks, it is desirable to implement some transceivers monolithically with the help of improving large-scale low-cost integration technology. Frequency synthesizers are an integral part of any transceiver systems for the generation of the local oscillator (LO) that is used for the up/down conversion of radio frequency (RF) signals from/to intermediate frequency (IF) or base-band signals. Even though frequency synthesizer theory is very mature, there is still a large research effort aimed to improve performance and optimize implementations for new technologies and emerging standards. One of the main drivers for research and technical advancements in frequency synthesizers is for the need to generate increasingly higher frequencies while decreasing power consumption. From the cost and area perspective, latest lowest transistor size based ASIC tool, reduced supply voltage, reduced component count on the chip design is important. The thesis was carried out with UMC O.18 um technology with 1 volt supply voltage. To reduce the power consumption more, the most power hungry block, prescaler was designed with TSPC based design with DTMOS technique. DTMOS technique was also applied in the amplifier design. Ring oscillator was designed instead of conventional LC tank to reduce the area of the chip and thus to serve the cost effectiveness. The overall power consumption was measured around 29m W
650		0	_aFrequency synthesizers
700	0		_aLertsak Lekawat, _eChairperson
700	0		_aApinunt Thanachayanont, _eExamination committee
700	0		_aChumnarn Punyasai, _eExamination committee
710	2		_aAIT Fellowship, _eScholarship donor
810	2		_aAsian Institute of Technology. _tThesis ; _vno. ME-07-05
856			_3Full-Text _uhttp://203.159.5.9/ait-thesis/detail.php?q=B23140
907			_a.b12052590 _bmnait _cu
902			_a251128
998			_b0 _c090414 _dm _ea _fu _g0
945			_lmnait
945			_lmnarc
942			_c22
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