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008			090414s2007 th uu|m rtt 0| a1eng d
035			_a.b12052607
099		9	_aAIT Thesis no.ME-07-06
100	0		_aWasit Limprasert
245	1	0	_aNoise reduction system for digital hearing aid
260			_aPathum Thani, Thailand : _bAsian Institute of Technology, _c2007
300			_a84 p. : _bill.
490	1		_aThesis ; no. ME-07-06
500			_aA thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Microelectronics, School of Engineering and Technology
502			_aThesis (M.Sc.) - Asian Institute of Technology, 2007
520			_aOne of the major problems for hearing aid users is surrounding noise. The thesis objective is to design noise reduction hardware (integrated circuit) for digital hearing aids. Instead of relying on separate algorithm and hardware (integrated circuit) developments, a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time is illustrated. A noise reduction core using ADMA adaptive Beamformer is designed and tested as an example
650		0	_aHearing aids _xNoise
650		0	_aNoise control
700	0		_aLertsak Lekawat, _eChairperson
700	1		_aAfzulpurkar, Nitin V., _eCo-Chairperson
700	0		_aPasin Israsena, _eExamination committee
710	2		_aGovernment of Thailand, _eScholarship donor
810	2		_aAsian Institute of Technology. _tThesis ; _vno. ME-07-06
856			_3Full-Text _uhttp://203.159.5.9/ait-thesis/detail.php?q=B11104
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902			_a240328
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