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035			_a.b11900210
099		9	_aAIT Thesis no.TC-02-08
100	1		_aMansur, Al
245	1	0	_aPerformance evaluation of Dual-Banyan ATM switch
260			_aBangkok : _bAsian Institute of Technology, _c2002
300			_a62 leaves
490	1		_aThesis ; _vno. TC-02-08
500			_aA thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Engineering and Technology
502			_aThesis (M.Eng.) - Asian Institute of Technology, 2002
520			_aBuffered Banyan network based ATM switches, which have been studied extensively in the recent past, are popular among switch designs because of their self-routing property, high degree of parallelism, regularity in architecture, constant delay for all input-output port pairs, in-order delivery of cells, and suitability for VLSI implementation. The performances of Dual-Banyan (DB) switch, internally speeded-up and dual planed DB switch have been studied in this thesis. Simulation tool for evaluating the performance of these three switches was developed. Switch performances are evaluated under uniform and single-source-to-single-destination traffic pattern where the cell arrival is modeled according to Bernoulli and Interrupted Bernoulli process. Maximum throughput is found to be only 0.25 in Dual-Banyan switch under Bernoulli arrival and maximum conflict traffic pattern whereas maximum throughput is about 0.5 in speeded-up switch and in dual plane switch under the same input traffic. Under bursty input traffic, it is found that dual plane switch has better throughput performance than other two architectures. Mean delay performance of the speeded-up switch and the dual plane switch is almost similar and is better than that of DB switch. For buffer size of eight in each switching stage and offered traffic load of 0.9, throughput is about 0.7, 0.6 and 0.5 in dual plane, speeded-up and DB switch respectively. It is observed that cell loss in each switching stage is different and depends on the input traffic and buffer size. In a DB switch, the stage at which largest cell lost occurs shifts with the increase of buffer for uniform traffic of moderate load. Under maximum conflict traffic pattern, the second stage has the highest loss and switch throughput is mostly determined by this stage in all three switches of size 32x32. Speeded-up switch has largest cell loss in its last stage and blocking is reduced significantly when more buffers are allocated in the last stage. For studied cases with a given input traffic and total buffer, buffer combinations for minimum blocking have been found.
650		0	_aAsynchronous transfer mode
650		0	_aTelecommunication _xSwitching systems
700	1		_aErke, Tapio J., _eChairperson
700	1		_aAhmed, Kazi Mohiuddin, _eExamination Committee
700	1		_aFernando, W.A.C., _eExamination Committee
710	2		_aGovernment of Finland, _eScholarship donor
810	2		_aAsian Institute of Technology. _tThesis ; _vno. TC-02-08
856			_3Full-Text _uhttp://203.159.5.9/ait-thesis/detail.php?q=B07559
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902			_a240710
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