Thesis (M.Eng.) - Asian Institute of Technology, 2003

The Rijndael Advanced Encryption Standard (AES) is worldwide known as the new latest secret key cryptography. This algorithm was developed to enhance the security of secret information sent through the open channel. In this thesis, AES hardware was implemented using both Xilinx FPGA technology and 0.35-om CMOS standard cell ASIC design. The goal is to propose efficient hardware implementation of the AES Rijndael with a 128-block length of plaintext and secret key. The design was also implemented to support Smart Card Applications, which require a smaller area and less power consumption of the circuit. There were three important parts to construct the AES algorithm including Encryption, Decryption, and Key Expansion. Encryption and Decryption data paths were resourcefully combined and share some resources with one another. Therefore, an order of arithmetic functions was revised, but the proper function still remained. The S-box and Inverse S-box used in the Encryption and Decryption respectively were critical to minimize the cost of circuit area. A composite field technique were proposed to integrate S-box and Inverse S-box and to reduce a multiplicative inverse table Y4 times smaller than a look-up-table method. Using a factoring technique, Mix and InverseMix Columns were merged to the same circuit and also used to perform functions for both Encryption and Decryption. The circuit, then, was implemented by reducing the cost of area. Considering the Key Expansion data path instead of using large memory (176 bytes) to collect the whole sub keys, an on-the-fly key technique was applied to reduce the number of mem01y and deliver the sub keys without storing the entire round keys. The architecture of AES algorithm was presented including 8-bit and 32-bit bus width. Both architectures were applied with the same techniques to reduce the cost of area as stated. The performance of the circuit was expressed in the values of the following parameters; Power Consumption per Operation, Area Time, Area Time Power, and Throughput per Area. In addition, the perfo1mance value of each design was presented by the summation of parameters multiplied by weighting factors. Comparisons of the values of both architectures, which are the result of testing and simulated measurement, indicate that the architecture of 32-bit bus width provides an appropriate high-speed data rate, less power consumption, and small area. Consequently, the 32-bit design meets specifications for Smart Card Applications.

A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies